A Closed-Form Transient Joule Heating Model for an Interconnect in an Integrated Circuit

Front and back ends of line (FEOL and BEOL) self-heating and mutual heating are important barriers to a sustained increase in processor speed and density. In this context, the severity of transient Joule heating in scaled interconnects under a variety of operating conditions (e.g., frequency and duty cycle) is not fully understood. Here we introduce the closed-form analytical transient Joule heating model to calculate the time-dependent temperature rise of an interconnect (ΔT
_Int
(t)) located at an arbitrary metal level within an integrated circuit (IC). The model is validated by high-fidelity finite element method simulations and specially designed test structures. Remarkably, the model predicts I
_Max
(the interconnect-specific current for a certain degree of ΔT
_Int
) within 20%-25% for an arbitrary duty cycle. Therefore, our model can be used to accurately predict temperature-accelerated interconnect reliability issues of a modern IC.