New Insight Into Negative Bias Temperature Instability Degradation During Self-Heating in Nanoscale Bulk FinFETs

In this letter, we investigate the threshold voltage shift (ΔV
_th
) by negative bias temperature instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk p-FinFET. To analyze the effect of NBTI in the presence of the SHE, the DC stress was performed under high-bias conditions, i.e., gate bias V
_GS
= -1.3 V and drain bias V
_DS
up to -1.3 V at room temperature, which was usually referred to as hot-carrier degradation (HCD) stress. It has been observed that the long-time (10 s ~ 10
³
s) power-law time exponent (n) decreases as VDS increases, and n was very close to that of NBTI-induced ΔV
_th
rather than HCD-induced ΔV
_th
at V
_GS
= V
_DS
= -1.3 V. For the first time, computer-aided design simulations were performed in combination with SHE and NBTI. The effect of NBTI in p-FinFET is confirmed to contribute significantly to ΔV
_th
under DC HCD stress because of SHE. The influence of SHE is mitigated in high-frequency circuit operation, but special attention should be paid to NBTI issues due to the potential occurrence of SHE as the technology nodes shrink.