Gate Insulator Engineering in Top-Gated Indium-Tin-Oxide-Stabilized ZnO Thin-Film Transistors

This letter proposes a high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO
₂
stack for thin-film transistors (TFTs), which contains a layer of SiH
₄
-sourced PECVD SiO
₂
(SiH
₄
-SiO
₂
) with a layer of tetraethyl-orthosilicate (TEOS)-sourced PECVD SiO
₂
(TEOS-SiO
₂
) underneath. The issues of high hydrogen content in the SiH
₄
-SiO
₂
and rich hydroxyl groups in the TEOS-SiO
₂
were found to be well addressed by capping the TEOS-SiO
₂
with SiH
₄
-SiO
₂
. Moreover, the electrical properties of the SiO
₂
stacks were shown to be strengthened in comparison with their single-layer counterparts. This is owing to the mutual interactions between hydrogen groups in the SiH
₄
-SiO
₂
and hydroxyl groups in the TEOS-SiO
₂
. Top-gated indium-tin-oxide-stabilized ZnO TFTs with stacked gate insulators (GIs) were demonstrated after the optimizations of the GI layer thickness and deposition order and were shown to be free of hysteresis with a high ON-OFF ratio of over 10
¹⁰
and a sharp subthreshold swing of 96.9 mV/decade. The combination of TEOS-SiO
₂
and SiH
₄
-SiO
₂
initiates an economical strategy to achieve reliable GIs for high-performance top-gated metal-oxide TFTs.