A Non-Hysteretic Sub-60-mV/decade Subthreshold Slope and ON-Current Boosts in Electrostrictive-Piezoelectric Transistors

Sub-60-mV/decade subthreshold slope (SS) without the cost of hysteresis using smart electrostrictive-piezoelectric gate insulator of a field-effect transistor is presented. This exploits a combined effect of linear and non-linear electromechanical coupling of piezoelectricity and electrostriction in a gate insulator of the transistor. The electrostrictive-piezoelectric insulator in a gate stack of a transistor results in negative capacitance with an internal charge amplification, leading to a large on-current boost and sub-60-mV/decade SS in the transistor characteristics. Using load-line analysis and capacitance tuning of electrostrictive-piezoelectric gate insulator and semiconductor channel capacitors, the possibility of eliminating hysteresis in the device characteristics of sub-60-mV/decade steep transistors is discussed. The steep SS and the on-current boost can potentially enable the reduction of operating voltage of the transistor.