A New Quality Metric for III–V/High-k MOS Gate Stacks Based on the Frequency Dispersion of Accumulation Capacitance and the CET

This letter proposes a metric to assess the quality of high-k dielectrics on III-V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, V
_t
. The metric is based on a capacitive equivalent thickness (CET) - normalized frequency dispersion (Deff) evaluated in the accumulation region of capacitance- voltage (C-V) measurements of III-V MOS devices. D
_eff
is found to be CET independent, which allows for a preliminary assessment of the dielectric quality by using relatively thick layers. Several gate stacks, single layer or bi-layer, including those with Al
₂
O
₃
, and the recently reported ASM-imec interfacial layer (IL) with HfO
₂
are evaluated and compared against Si MOS devices. Using the proposed technique, a clear difference between the various deposition processes is observed. The results indicate that the quality of a single layer Al
₂
O
₃
or a bi-layer stack of Al
₂
O
₃
/HfO
₂
on InGaAs is significantly lower compared with Si gate stacks while the ASM-imec IL yields a gate-stack with good performance on the proposed quality metric. In addition, these results correlate well with the reliability performance of the studied gate stacks.