I. Introduction
Strain engineering is a crucial technology to provide enhancement of carrier velocity in scaled Si transistors through specific manipulations of their bandstructure [1], [2]. The state-of-the-art strain techniques are mostly based on the deposition of contact etch-stop layers (CESL), by depositing source and drain (S/D) from a lattice mismatched semiconductor (e.g., SiGe, Si:C), or at the wafer level, by growing strained Si on a strain-relaxed-buffer (SRB) [3]–[6]. Xu et al. have shown that S/D stressors deliver more strain in a Fin than CESL, though in both cases, the maximum achieved stress amounts less than 0.5 GPa [7]. In turn, Eneman et al. reported that strained Si grown on SRB is the most effective technique to induce tensile stress in Fins for the 14 nm and smaller nodes, although epitaxial Si:C S/D stressors are required to achieve such high stress levels [8], [9]. However, because of the constrained geometry, such methods become difficult to implement and often ineffective for the presently employed Fin architecture featuring 22 nm and smaller gate lengths [6]–[9].