Multilayer MoS2 Thin-Film Transistors Employing Silicon Nitride and Silicon Oxide Dielectric Layers

Bottom-gate molybdenum disulfide (MoS
₂
) TFTs, having plasma-enhanced chemical vapor deposition (PECVD) gate-dielectric thin films, were fabricated from 80-100 nm thick mechanically exfoliated MoS
₂
multilayers. Three separate gate dielectric structures were investigated consisting of: 1) a single PECVD SiN
_x
layer; 2) a dual PECVD SiO
_x
/SiN
_x
layer; and 3) a reference thermal SiO2 layer. The devices fabricated on the bi-layer dielectric had a field-effect mobility (μ
_e
) of ~12 cm
²
/Vs and an ON/OFF ratio of ~10
⁵
, while the TFTs on SiN
_x
or thermal SiO
₂
dielectric had μ
_e
~ 4 to 5 cm
²
/Vs and an ON/OFF ratio ~10
⁴
to 10
⁵
. The calculated interface trap density for the bi-layer dielectric devices was found to be 10× less than the SiN
_x
devices and 2x less than the thermal SiO
₂
devices. The variation in the defect density was due to localized trap states in the dielectric/semiconductor interface.