Gate Dielectric Leakage Reduction in Hard-Mask Defined and Dry-Etch Patterned Organic TFTs Devices

To control the parasitic conduction between devices, photolithography and dry etching of organic thin-film transistors (OTFTs), which utilize the gate metal as a hard-mask for organic semiconductor (OSC) patterning, are used. This study shows that the hard-mask patterning process results in a gate leakage current, which is attributed to the sidewall defects. The characteristic mechanisms of different leakage currents were studied to understand this behavior, including negative-bias temperature stress (NBTS) testing and measurements of devices with structural asymmetry. Additionally, an optimized structure design is proposed to suppress the leakage and increase the reliability of OTFTs. Such improvements are necessary for practical applications of OTFTs requiring small channel widths, such as displays and logic circuitry.