Highly-Doped Region Optimization for Reduced Hot-Carrier Effects in Dual-Gate Low Temperature Polysilicon TFTs

In this study, dual-gate thin-film transistors with low-temperature polysilicon as the active channel layer are thoroughly investigated. Under a large current operation where a high voltage is applied, impact ionization occurs near the drain, generating a large number of electron-hole pairs. Owing to the positive bias applied to the gate and drain, holes accumulate on the backside of the channel, which causes an earlier turn-on in the sub-channel, as is observed in the I-V characteristics of the saturation region. By enlarging the highly doped region between the double gates in the channel, the threshold voltage shift can be completely suppressed, and the leakage current rise can be reduced. The electric field simulation using Silvaco TCAD was consistent with the experimental results. Finally, a series transistor structure is used to measure the impact after the operation condition and further verify the physical model.