Strategies for a Wide Memory Window of Ferroelectric FET for Multilevel Ferroelectric VNAND Operation

Basic gate stack structure of the Ferroelectric FET is Metal-ferroelectric-insulator-silicon (MFIS), where the memory window (M.W) is
$2^{\ast } $
(Pr-Q
$_{\text {it}}\text {)}$
/CFE considering the trapped charge. However, in Metal - insulator - ferroelectric - insulator - silicon (MIFIS) gate-stacked FeFETs, the M.W is
$2^{\ast } $
{(Pr-Q
$_{\text {it}}\text {)}$
/C
$_{\text {FE}} +$
(Q’it-Q
$_{\text {it}}\text {)}$
/C
$_{\text {G. {IL}}}\text {)}$
}, which allows the M.W to widen in case the Q’it injected from the gate side is larger than the Qit injected from the channel side. In this letter, we propose a band engineered (BE) gate insulator in MIFIS gate-stacked FeFETs. This lowers the energy barrier of the hole when applying the program voltage, thereby increasing the amount of hole injected from the gate side, and consequently widening the M.W. Furthermore, it is demonstrated by TCAD simulation that the physical origins of Vt shift of PGM state is hole injection. In addition, in the case of BE-MIFIS gate-stacked FeFETs, the maximum ISPP slope is increased by about 2 times compared to conventional MIFIS, which is an important feature in ferroelectric VNAND (FeVNAND) operated at low voltage.