Analysis of Degradation Mechanism in Poly-Si TFTs Under Dynamic Gate Voltage Stress With Short Pulse Width Duration

Degradation behaviors of polycrystalline silicon thin-film transistors under dynamic gate voltage stress with short pulse width duration are systematically investigated for the first time. Both the peak voltage duration and the base voltage duration have an impact on the hot carrier degradation of the device. Incorporated with simulations, an advanced model for nonequilibrium junction degradation is proposed.