Design Strategy to Improve Memory Window in Ferroelectric Transistors With Oxide Semiconductor Channel

Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because
${n}$
-type oxide semiconductors cannot provide sufficient hole carriers to realize ferroelectric polarization switching. To solve this issue, a novel design strategy is proposed to achieve increased polarization switching while maintaining the stability of oxide semiconductor-based ferroelectric thin-film transistors (FeTFTs). By inserting an additional
${p}$
-type CuOx layer between the
${n}$
-type oxide semiconductor InZnOx and ferroelectric HfZrOx, increased polarization switching is achieved owing to the high electron and hole densities in the InZnOx and CuOx layers, respectively. Thus, a memory window of 4 V is achieved, which cannot be obtained using a single oxide-semiconductor channel. We also demonstrate that the proposed method is viable for three-dimensional ferroelectric NAND (3D FeNAND) devices. In 3D FeNAND, replacing the dielectric filler with
${p}$
-type CuOx maximizes polarization switching and enlarges the memory window. The results demonstrate a novel structure and fabrication method for high-performance FeTFTs for advanced 3D non-volatile memory applications.