I. Introduction
THE ERROR correcting code in a magnetic recording application must meet stringent error-floor and throughput requirements at a relatively large block length; the sector size for hard disk drives is typically 32768 bits, and the throughput can be 2 Gb/s or more. Regularity in the structure of the encoder/decoder facilitates hardware implementation by reducing interconnect congestion and processing requirements [1]. There has been significant research into finding regularly structured codes. For example, to avoid the high complexity of the early low-density parity check (LDPC) codes, which were random, different structured codes such as quasi-cyclic LDPC codes [2] emerged after their rediscovery in [3] and secured their place in different standards such as IEEE802.11n [4] and IEEE 802.16e [5].