Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays

Neural networks have been used for a long time for image detection and recognition applications due to their ability and efficiency in complex problem solving. Several researchers have chosen to design and develop hardware accelerators for the convolution layer due to the large computational expense consumed by this layer. For that reason, a system that performs indirect GEMM convolution is implemented in a FPGA in this letter. Thus, the input data is segmented and distributed into acceleration modules in a parallel and distributed manner using the Network-on-Chip (NoC) paradigm, and a systolic array (SA) is implemented for the matrix multiplication operation as processing blocks within each NoC Node. Synthesis and performance results show that the implementation of this system presents better results compared to the state of the art in areas, such as acceleration factor, consumption of resources, latency, and operational frequency.