SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC

Networks-on-chips (NoCs) are widely used for on-chip communications in embedded multiprocessor architectures. SMART NoC achieves ultralow latency by enabling single-cycle multiple-hop transmission via bypass channels. However, the contention on the bypass channels seriously degrades the performance of SMART NoC by breaking the bypass paths. Therefore, contention-free task mapping and scheduling are essential for optimal system performance. In this letter, we propose an satisfiability modulo theories (SMTs)-based framework to find the contention-free task mapping with the minimum application schedule length. On top of the SMT’s fast reasoning capability for the conditional constraints, we develop efficient search-space reduction techniques to achieve practical scalability. Experiments demonstrate that our approach achieves
$10\times $
higher scalability compared to integer linear programming (ILP) approach with
$599.5\times $
faster average runtime for finding an optimum solution.