Understanding Metastability in SAR ADCs: Part II: Asynchronous

This article is the second part of our tutorial on metastability in successive approximation register (SAR) analog-to-digital converters (ADCs). Having covered the synchronous topology in Part I in the Spring 2019 issue of IEEE Solid-State Circuits Magazine, we now investigate its asynchronous (or self-timed) counterpart. Even though the idea of successive approximation is rather old, it was not until 2006 that the benefits of asynchronous timing were unleashed through a seminal contribution by Chen et al. [1]. Since then, the asynchronous variant has emerged as a very popular option to achieve higher speeds and tame metastability issues more gracefully. The latter aspect is the focus of this article.