I. Introduction
Multimode multicorner timing-driven design optimization aims at satisfying timing constraints in all modes and corners, while improving the area and power performance of the design [1]. Fixing a violation in one timing scenario is likely to cause a new violation in another. This problematic behavior is accentuated when power also needs to be optimized, since the worst-case power corner could be different from the worst-case timing corner. Such a multiobjective problem is inherently complex and computationally challenging, when considering the highly increasing number of mode/corner combinations. Over the years, multiple optimization methods have been introduced to achieve significant power–performance–area (PPA) improvement. Cell sizing, transistor voltage threshold selection (-swap), netlist restructuring, timing-driven cell relocation, useful clock skew, and buffer insertion/deletion are just a few examples of optimization methods supported by modern physical design tools [2].