I. Introduction
As feature size of semiconductors enters nanometer era, lithographic process variations (PVs) are emerging as more severe issues in chip manufacturing process. That is, these PVs may result in manufacturing defects and a decrease of yield. Besides some design for manufacturability (DFM) approaches, such as multiple patterning and litho-friendly layout design [1], [2], a de facto solution alleviating variations is mask optimization through various resolution enhancement techniques (RETs) (e.g., [3], and [4]). Optical proximity correction (OPC) is the most successful representative strategy among numerous RETs, which aims at compensating lithography proximity effects by correcting mask pattern shapes and inserting assist features.