Density-Uniformity-Aware Analog Layout Retargeting

To enhance yield of fabricated chips, foundries normally insert dummy features to tape-out-ready layouts in order to improve pattern density uniformity. This process may unfortunately degrade the performance of analog/radio-frequency and high-speed digital integrated circuits. In this paper, we investigate the ways how to control pattern density distribution on different layers in analog layouts during the process of layout migration from an old technology to a new one or for design specification update in the same technology. We develop a new set of schemes for smartly modifying layout elements to improve pattern density uniformity besides the traditional dummy-insertion operation. The experimental results show that our proposed approach can account for up to 80% improvement toward the ideal density uniformity in the regular analog layouts. This promising option can significantly decrease the coupling-capacitance-induced parasitic effects due to the traditional sole dummy-insertion operation.