I. Introduction
Logic synthesis based on Exclusive-OR (EXOR) sums can reduce gate counts and has application in various technologies, making it an active area of research. Previously, reversible three-level logic synthesis based on products of EXOR sums of inputs (POE) was explored as a means to reduce cost [1] in no-ancilla-line reversible and quantum permutative circuits [2]. The mathematical representation of POE (EXOR-AND) expressions is based on the Galois field 2 [GF(2)] linear transform approach used by Meinel and Theobald [3], Günther and Drechsler [4], and Karpovsky et al. [5]. In a different line of research pioneered by Luccio and Pagli [6] irreversible three-level logic synthesis is based on a pseudoproduct EXOR-AND formulation. Later works applied the pseudoproduct formulation to heuristic logic synthesis methods [7]–[9] for EXOR-AND-OR circuits, and these methods consistently produce more compact expressions than AND-OR sum of products (SOP) logic synthesis methods. In CMOS technology this correlates to reduced area, capacitance, and dynamic power consumption.