Accelerating Architectural Simulation Via Statistical Techniques: A Survey

In computer architecture research and development, simulation is a powerful way of acquiring and predicting processor behaviors. While architectural simulation has been extensively utilized for computer performance evaluation, design space exploration, and computer architecture assessment, it still suffers from the high computational costs in practice. Specifically, the total simulation time is determined by the simulator's raw speed and the total number of simulated instructions. The simulator's speed can be improved by enhanced simulation infrastructures (e.g., simulators with high-level abstraction, parallel simulators, and hardware-assisted simulators). Orthogonal to these work, recent studies also managed to significantly reduce the total number of simulated instructions with a slight loss of accuracy. Interestingly, we observe that most of these work are built upon statistical techniques. This survey presents a comprehensive review to such studies and proposes a taxonomy based on the sources of reduction. In addition to identifying the similarities and differences of state-of-the-art approaches, we further discuss insights gained from these studies as well as implications for future research.

I. Introduction

When designing a processor, designers have to estimate architectural behaviors of the design before implementation and manufacture, so that the processor can meet specific design objectives. As one of the most prevalent methodologies for addressing this problem, architectural simulation has been extensively deployed since it offers designers a balance of cost, timeliness, and flexibility [1]. Application scopes of architectural simulation include but are not limited to performance evaluation, functional validation, design space exploration (DSE), and assessment of architectural innovations. In industry, all leading processor manufacturers have devised their own cycle-accurate simulators to the design of processor. For example, IBM maintains Mambo simulation environment [2], which is designed for IBM PowerPC systems, ranging from embedded system (e.g., IBM’s 32-bit embedded 405GP [3]) to supercomputer (e.g., BlueGene). AMD develops SimNow simulator [4] that emulates AMD Athlon 64 and AMD Opteron uniprocessor and multiprocessor systems. Intel also uses HAsim [5] to evaluate future processor products. Architectural simulation also plays a critical role in academic research of computer systems, since it enables validations of novel research ideas without manufacturing real chips. One piece of evidence is that more than 80% papers presented at premier conferences of computer architecture research, ISCA/HPCA/Micro (2009–2011), utilized architectural simulators to validate the proposed ideas.