Fast Aging-Aware Timing Analysis Framework With Temporal–Spatial Graph Neural Network

With the downscaling of CMOS technology, device aging induced by hot carrier injection and bias temperature instability effects poses severe challenges to timing analysis of digital circuits. In this work, a fast aging-aware timing analysis framework based on temporal–spatial graph neural network (GNN) is proposed for the first time. The temporal–spatial GNN takes gated tanh unit (GTU) as the temporal network to extract devices’ degradation from dynamic biases, and takes inductive GraphSAGE as the spatial network to obtain whole graph information from circuit topology and output circuit aging delay. With comprehensive comparison among the network candidates, the combination of GTU and GraphSAGE presents the highest accuracy in predicting the standard cell aging delay. Owing to the superior features capture capability, this framework significantly improves the aging prediction efficiency under various operation conditions, especially facing the iterations of usage scenario, design version and process design kit. Compared with the conventional flow, the average acceleration ratio of our temporal–spatial network in predicting aging delay is more than 200 times. Furthermore, this framework is demonstrated with ADDER and FIFO circuits in timing analysis at the end of life. Thus, this work is helpful to the aging-aware circuit design in nano-scale technology.

I. Introduction

With the rapid technology evolution of digital integrated circuits, the impact of device aging on circuit performance becomes more and more significant [1]. The aging effect of MOSFETs mainly includes bias temperature instability (BTI) and hot carrier injection (HCI), as shown in Fig. 1. The BTI effect is due to the charge trapping at or near the gate oxide/substrate interface, while the HCI effect is originated from the interface states and oxide traps generation induced by hot carriers accelerated by transverse electric field. Both BTI and HCI effects are sensitive to device sizes ( and ) and stress biases ( and ). The two aging effects will lead to the device parameters shifts, such as threshold voltage and drive current, which further increase the propagation delay of the cell circuit. In addition, this negative impact on the critical path delay of the digital circuit will eventually result in timing violations and circuit faults. To fastly and accurately estimate the circuit performance degradation during design phase, it is a big necessity to establish an aging-aware timing analysis methodology of digital circuits. However, this faces great challenges due to the increasing scale of digital circuit and multiple iterations of design version and process design kits. Fig. 1.

Left half of the figure shows BTI and HCI aging effects of MOSFET. The right half shows how stress bias ( and ) and static parameters ( and ) can finally affect the circuit delay.