Parallel Static Learning Toward Heterogeneous Computing Architectures

Static learning is a learning algorithm for finding additional implicit implications between gates in a netlist. In automatic test pattern generation (ATPG) the learned implications help recognize conflicts and redundancies early, and thus greatly improve the performance of ATPG. Though ATPG can further benefit from multiple runs of incremental or dynamic learning, it is only feasible when the learning process is fast enough. In this article, we study the performance optimization of static learning through parallelization on heterogeneous computing architectures, which includes multicore microprocessors (CPUs), and graphics processing units (GPUs). We discuss the advantages and limitations of each of these architectures. With their specific features in mind, we propose two different parallelization strategies that are tailored to multicore CPUs and GPUs. Speedup and performance scalability of the two proposed parallel algorithms are analyzed. It is demonstrated that for million-gate designs, close to linear performance gain is achieved on multicore CPUs, and up to
$260\times $
speedup over a commercial tool can be obtained on a single graphic card.