TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA

Coarse-grained reconfigurable architectures (CGRAs) are energy-efficient and processing-flexible platforms to perform parallel computation. CGRAs combine the advantages of flexibility of general-purpose processors (GPPs) and energy efficiency of application-specific integrated circuits (ASICs). During the compilation process, the CGRA compiler needs to convert the high-level language codes into a data flow graph, and then map it onto CGRA to generate instruction flow and configuration context. The instruction mapping schemes of the CGRA compiler have a great impact on the efficiency and energy consumption of CGRAs. Furthermore, the quality of the instruction mapping schemes of the CGRA compiler highly depends on how the compiler maps data dependencies using different CGRA resources. This article proposes an enhanced transfer-aware loop mapping method, TAEM 2.0, based on state-of-the-art TAEM algorithm. Based on a parallel iterative IBBMCX algorithm and comprehensive CGRA resources analysis strategy, this method efficiently processes the complex situations of utilizing all those heterogeneous resources on CGRA and significantly accelerates the compilation process. Experimental results show TAEM 2.0 can accelerate the compilation process by $4.40\times $ while generating the same or better mapping results on CGRA, when compared to the state-of-art mapping technique.

I. Introduction

With the development of technologies, such as neural networks and big data, the demand for hardware resources for applications is constantly developing in the direction of large-scale, large-capacity, and fast computing. Generative pretrained transformer 3 (GPT-3) [2], the third-generation language prediction model in the GPT-n series created by OpenAI, has a capacity of 175 billion machine learning parameters, and has been trained about 45 TB of text data from multiple sources which include Wikipedia and books. The training overhead of GPT-3 is flops, which will take about 3200 TitanX GPUs for one year of training. The huge demand for hardware resources boosts the urgent requirement for innovations in hardware architectures. As a result, as shown in Fig. 1, coarse-grained reconfigurable architecture (CGRA) [3], [4], [5], [6], [7], [8], an energy-efficient and processing-flexible parallel hardware architecture is designed. CGRAs combine the advantages of flexibility of general-purpose processors (GPPs) and energy efficiency of application-specific integrated circuits (ASICs), and are popular for multimedia and AI applications [3], [4], [5], [6], [7], [8]. Fig. 1.

Architecture of a CGRA with a PEA.