Geometric Programming Approach to Glitch Minimization via Gate Sizing

The problem of gate sizing to meet timing specification while minimizing functional power/area is well understood and is solved by the use of geometric programs (GPs). While these area minimization GP (AM-GP) formulations minimize functional power, they do not address the problem of glitches. Glitches are extraneous transitions caused by signal arrival time imbalance at the input nodes of logic gates. A gate sizing algorithm, area-glitch minimization GP (AGM-GP), is proposed to reduce glitches while constraining area and adhering to a timing specification. Glitch reduction is achieved through signal arrival time balancing posed as posynomials in a GP formulation. Prior art does not exploit the complete power of gate sizing when reducing glitches in an attempt to meet the timing specification. In particular, the proposed formulation allows both upsizing and downsizing without causing any timing violation, at the expense of a marginal increase in area. Traditional downsizing methods can be used to further reduce glitches over and above the AGM-GP solution. Simulation results on the ISCAS-85 benchmark circuits show an overall reduction of 20.4% glitch power and 9.5% total power which is, respectively, 13.8% and 3.9% better than just downsizing the AM-GP solution. This power reduction was achieved with an average area increase of 4.2%.

I. Introduction

Technology scaling has enabled modern-day microprocessors to function at very high speeds. However, this advancement has come at the cost of increased power and energy dissipation. The power consumed by a digital circuit can be split into two components: 1) static and 2) dynamic power. Static or leakage power is consumed by a digital circuit as long as it is powered on even if the inputs do not toggle. On the other hand, the dynamic power is consumed when the inputs to the circuit toggle, causing a subset of logic gates to undergo transitions at their output. These transitions can be of two types: ones which are essential for circuit functionality known as functional transitions and others which are nonessential transients known as glitches.