I. Introduction
As device feature sizes continue to rapidly decrease, the interconnecting delay is becoming a bottleneck limiting IC performance. The three-dimensional integrated circuits (3D-ICs) technology involving vertically stacking multiple dies connected by through silicon vias (TSVs) provides a promising way to alleviate the interconnecting problem and achieves a significant reduction in chip area, wire length, and interconnect power [1]. Study indicates that the average wire length of a 3D-IC varies according to the square root of the number of layers. Moreover, 3D-ICs have the potential for heterogeneous integration, which is essential for the More than Moore (MtM) technology. 3D integration has already seen several commercial applications in the form of 3D memory but there are still existing significant open problems in both academia and industry [2]. In this work, we will focus on the TSV reliability problem.