A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance

True random number generator (TRNG) as one essential hardware primitive is widely used in cryptography, Monte Carlo simulation, and gambling. To evaluate the security of TRNG, the entropy of the TRNG’s output is usually estimated by the stochastic model in theory or measured off-chip after fabrication. However, the sufficiency of entropy is difficult to be guaranteed in practice due to the facts: 1) the inaccuracy of the model-based jitter measurement method; 2) the variations of the chip manufacturing process and operating environments (such as supply voltage and temperature); and 3) malicious attacks. In this work, we design a novel TRNG architecture with on-chip entropy assurance to properly solve practical security problems. In the design, we propose an on-chip entropy estimator for measuring independent jitter to quantify true randomness, which enables continuous monitoring of TRNG at runtime. Furthermore, with the cooperation of the proposed on-chip entropy estimator and a rational self-adaptive mechanism, the designed TRNG can steadily generate bitstreams with sufficient entropy (≥ 0.999 per bit) against PVT variations. We implement the TRNG architecture in FPGAs with different technology nodes (45 and 65 nm) and SMIC 130 nm chips. Experimental results validate that the designed TRNG has an excellent performance in terms of technology independence and environmental robustness. The generated bitstreams pass the NIST SP800-22 and Diehard statistical test suites successfully without any post-processing.