I. Introduction
Three-dimensional integrated circuits (3-D ICs) have new design parameters such as die-to-die bonding styles, through-silicon-via (TSV) types, TSV size, and the die count to be stacked. Therefore, 3-D ICs have much larger design space than traditional 2-D integrated circuits (2-D ICs), so the need for fast estimation of the quality (area, delay, power, etc.) of 3-D ICs is increasing for early design space exploration. Among various quality estimation methodologies such as system-level modeling and fast prototyping for early-stage design space exploration, using wirelength distribution models is widely and frequently used because the models are simple, fast, sufficiently accurate, and easy to use.