SFCache: Hybrid NF Synthesization in Runtime With Rule-Caching in Programmable Switches

Data plane programmable (PDP) switches are becoming increasingly popular for network function virtualization (NFV), for their programmability and high packet processing performance. However, the inherent limitations of PDP switches, such as limited memory space, make it challenging to implement certain types of network functions (NFs) (i.e., the stateful ones) on them. This paper proposes SFCache, which combines PDP switches and commodity servers to achieve self-adaptive SFC deployment. SFCache aims to exploit the high packet processing performance of PDP switches while supporting the flexible deployment of a wide range of SFCs (including the stateful ones) with servers. Specifically, SFCache can dynamically improve the packet processing performance of the SFCs that were deployed on servers by selectively caching SFC-level packet processing rules on PDP switches. We design a few key components to facilitate SFCache, including an NF-destructed P4 pipeline that allows customizing packet processing rules in a match-rewrite pattern, a runtime NF synthesis method that can transform a set of NF-level match-rewrite rules into an equivalent SFC-level rule, and a count-min selection strategy to choose the best synthesized rule for being cached in PDP switch pipeline. We prototype SFCache with a PDP switch based on Tofino ASIC and a server, and demonstrate the effectiveness of our proposal experimentally.