Low Complexity Transmitter Architecture for SC-FDMA Systems With SFBC Code

In this letter, a novel low complexity transmitter architecture is proposed for a space frequency block coding (SFBC) single carrier frequency division multiple access (SC-FMDA) system, where the transmitted signals for each antenna are generated using a time-domain linear sequence combination (TDLSC) scheme. In the TDLSC method, a specific set of various transmitted signals is designed to reduce the peak-to-average power ratio (PAPR) without destroying the SFBC orthogonality and requiring no side information. Additionally, a low-complexity side information detection method is also presented. Computer simulations show that the PAPR reduction performance of the TDLSC outperforms the existing simplified selective mapping scheme and has a slight performance loss of less than 0.2 dB compared to an ordinary selective mapping scheme. The proposed side information detection method has a significantly lower complexity while achieving the same bit error rate performance compared to the selected mapping-based method with a maximum likelihood decoder.