A New Three-Phase Multipoint Clamped 5L-HPFC With Reduced PSD Count and Switch Stress

The tradeoff between advantages and the overall part count of classical multilevel converters are leading to an active interest on introducing a new topology with reduced power semiconductor device (PSD) count. In this paper, a new multipoint clamped three-phase five-level high-power-factor converter (5L-HPFC) is proposed. The converter can be modeled as a diode-clamped converter with omission of clamping diodes. The impact of voltage stress on PSDs with two pulsewidth modulation strategies is studied, and a methodology for reducing switch stress per each leg is presented. Comprehensive comparative analysis is carried out with existing topologies. The minimum value of normalized index makes the proposed topology suitable for medium-voltage and high-power applications. In addition, a new single-band hysteresis current controller (SBHC) is proposed and compared with conventional single-band and multiband current control techniques for ac-dc power conversion applications. Furthermore, the proposed topology with the SBHC is investigated under the following conditions: bidirectional power flow capability, supply unbalance, harmonics elimination, and power factor correction. The validation of a new 5L-HPFC with the proposed controlling scheme is verified with simulation and a downscaled experimental setup.