Peak Detector With an FPGA-Only Solution for Multichannel Ultrafast Signals

Peak detection is useful in a wide range of applications. To achieve this task, conventional approaches [including dedicated application specific integrated circuit-based designs] often demand
analog
readout chains and compulsory add-ons [e.g., additional analogy-to-digital converter (ADC) for peak sampling], rendering them neither compact nor flexible. In this article, we propose a field programmable gate array (FPGA)-only solution to fulfill this task without any external components. Specifically, we achieve peak detection with only a low-voltage differential signaling (LVDS) comparator and two general-purpose input/outputs (GPIOs). Therefore, one can flexibly make a practical deployment by a simple routing process, a nontrivial task even for inexperienced engineers. Meanwhile, to further compact the design for peak sampling, we leverage an FPGA-based slope ADC within which, we propose a new resource-efficient and calibration-free time-to-digital converter architecture. The underlying rational is to minimize the nonlinearity problem by squeezing all resources within a single clock region. We have implemented a prototype using Xilinx FPGA and extensively evaluated its performance in rather challenging scenarios. Results demonstrate a peak digitization error of only about 30 mV in a full 1.8 V range for impulses with as few as 10ns pulsewidth. Meanwhile, in a practical deployment that requires a wide range of peak sampling, the achieved energy resolution is only 1.3% worse than a dedicated high-speed oscilloscope.