A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling

PCI Express (PCIe) PHY is used for alternate protocols with memory and coherency semantics such as Compute Express link and Ultra-Path Interconnect due to its low latency and power efficiency. In this article, we propose mechanisms to use PCIe 6.0 PHY at 64.0 GT/s with PAM-4 signaling for coherency and memory protocols in platforms deploying heterogeneous processing elements and memory subsystems with 0 latency impact, high-bandwidth efficiency, and high reliability. We also propose a new L0p mechanism for power savings with low latency.