Contents I. Introduction
To support complex and spectrally efficient modulation schemes, such as high-order quadrature amplitude modulations (QAMs), around a millimeter-wave carrier, the transceiver local oscillator (LO) integrated jitter is required to be extremely low. For example, as discussed in [1], to enable a 64-QAM at 40 GHz carrier frequency, the LO rms jitter has to be lower than 89 fs, which is an extremely challenging design specification and can become the bottleneck of the overall transceiver chain. Moreover, to enable the ubiquitous diffusion of devices capable of wideband wireless connectivity, the transceiver cost has to be kept low. To achieve this, the LO has to be integrated in deep sub-micrometer CMOS technology, and the occupied silicon area has to be small. The conventional LO implementation, based on an analog type-II charge-pump (CP)-phase-locked loop (PLL), can achieve excellent integrated jitter performance, as demonstrated in [2]–[8]. However, the analog loop filter integrating capacitance is bulky and can occupy a significant silicon area with respect to other PLL sub-blocks. On the other hand, digital type-II PLLs are naturally suited for a small footprint, thanks to the digital implementation of the loop filter, which is more compact and easier to scale down in advanced CMOS technology nodes with respect to its analog counterpart [10]–[14]. Nevertheless, the PLL integrated jitter is ultimately limited by time-to-digital converter (TDC) quantization noise, which adds on top of intrinsic reference and oscillator phase noise [15], [16]. TDC quantization noise could be reduced by adopting a very fine time resolution, but this approach typically leads to a more complex design with increased area occupation and power consumption, especially if low integrated jitter is targeted [11]. An effective solution that regained popularity in recent years to achieve, at the same time, low integrated jitter and small PLL footprint is to rely on an analog type-I PLL architecture [17]–[30]. The analog implementation avoids quantization noise typical of digital PLLs, while the loop filter area occupation is modest, thanks to the absence of the integrating capacitance and the inherent superior stability of a type-I feedback loop [27]. Moreover, the design of a CP circuit is avoided, which would be especially cumbersome in deep sub-micrometer CMOS technologies due to the reduced supply voltage headroom. It is worth pointing out that digital PLLs could also be configured to operate in type-I, by disabling the integral path in the digital loop filter. This is typically done in PLLs that have to operate with very large bandwidth, for instance, to aggressively filter the oscillator phase noise, where loop stability becomes a primary concern, as in [31]. However, in contrast to analog PLLs, where a type-I implementation leads to practical advantages in terms of area occupation and simpler phase detector design, in digital PLLs it is straightforward to implement an integral part in the digital loop filter, so, unless necessary, type-I loops are seldom the preferred designer’s choice.
