I. Introduction
Energy efficiency is a crucial design aspect in battery-powered and power-limited systems [1]–[3]. Wide voltage scaling has been extensively exploited to improve the energy efficiency of digital sub-systems with low to moderately high complexity [3]–[10] (e.g., up to several hundreds of kgates), and hence potentially well-suited for low energy per operation. Wide voltage scaling quadratically reduces energy in the common case via ultra-low voltage operation, while achieving full performance at nominal voltage, when needed [3]–[10]. Under a wide voltage range, clock network optimization is challenging as the dominant clock skew contribution is different at different voltages. In particular, repeater insertion is largely determined by the balance between the wire and repeater delay, which is, in turn, sensitive to the supply voltage [10]–[13].