A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization

This paper presents a 0.5-V 12-bit low-voltage power-efficient successive-approximation register (SAR) analogto-digital converter (ADC) using an adaptive time-domain (ATD) comparator with noise optimization. To be power efficient with different residual input levels (ΔVin) during conversion, the proposed ATD comparator automatically adjusts its input-referred noise performance rather than consuming the same power for each bit conversion. Considering the noise requirement of 12-bit resolution, the proposed ATD technique effectively reduces the comparator power consumption by 50% compared to the conventional approach. Moreover, a differential threshold window (DTW) technique is also developed to provide the optimized time-domain threshold for lowest figure-of-merit (FoM) performance with a self-adjusted(V
_ctrlp
-V
_ctrln
), depending on process- voltage-temperature (PVT) variation. The test chip occupies a core area of 0.109 mm
²
in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology. With a 0.5-V supply voltage, the prototype consumes 810 and 1425 nW at 100 and 250 kS/s, respectively. The achieved effective number of bits and signal-to-noise and distortion ratio with Nyquist-rate input are 10.71/10.3 bit and 66.3/63.8 dB, respectively. The resultant Walden FoM and Schreier FoM are 4.82/4.52 fJ/conversion step and 174.2/173.23 dB, respectively.