I. Introduction
Implantable sensor nodes have demanded low-power implementation of high-resolution analog-to-digital converters (ADCs) for acquiring bio-potential signals of a few-kilohertz bandwidth. Successive approximation register (SAR) ADC [1]–[4] has been the most popular architecture in sensor applications thanks to superior energy efficiency and robustness against process/voltage/temperature (PVT) variations. In high-resolution applications, however, comparator noise eventually limits the maximum achievable effective-number-of-bits (ENOBs).