Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling

This paper introduces dynamically adaptable pipelines to enable microarchitecture-driven voltage scaling, adapting the microarchitecture to the most energy-efficient configuration for a time-varying throughput target or supply voltage requirement VDD. Dynamic adaptation of the pipeline depth is introduced to curtail the contribution that dominates the overall energy (e.g., dynamic, clock, and leakage), as dictated by the throughput target and VDD. Microarchitectural adaptation of the pipeline depth also flattens the energy dependence on VDD around the minimum-energy point, thus facilitating nearly minimumenergy operation in the presence of inaccuracies in VDD (e.g., discretization and non-idealities). Dynamically adaptable pipelines can be fully integrated with automated digital flows at design time and with dynamic voltage scaling schemes at run time. The proposed approach is demonstrated with a 256-point radix-4 fixed-point FFT engine on a 40-nm test chip. Measurements show energy savings up to 30% (38%) at isothroughput (iso-voltage) in an area and the maximum performance penalty of 5% and 11%, respectively.