A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology

This paper presents a six-transistor bitcell SRAM with pMOS access transistor. Utilizing pMOS access transistor results in lower zero-level degradation (ZLD) and, hence, higher read stability. In addition, the access transistor connected to the internal node holding VDD acts as a stabilizer and counter balances the effect of ZLD. In order to improve the writability, wordline (WL) boosting is exploited. WL boosting also helps to compensate the lower speed of the pMOS access transistor compared with nMOS transistor. To verify our design, a 2-kb SRAM is fabricated in the TSMC 65-nm CMOS technology. Measurement results show that the maximum operational frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/bit at 400 mV.