A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <–73 dBc Fractional Spur and <–110 dBc Reference Spur in 65 nm CMOS

This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is capable of suppressing both internal spur, i.e., fractional-N spur, and externally coupled spur from input paths. It can be further extended for multi-stage operation for mitigating multiple spur sources. Both theoretical analysis and simulation results are provided in this paper to explore the design tradeoffs of the proposed technique. A proof-of-concept prototype is implemented in 65 nm CMOS. It measures external spur reduction of 15 to 35 dB and the worst-case fractional spur of 73.66 to 117 dBc with 20-50 dB improvement after enabling the cancellation loop. The measured reference spur ranges from 110.1 to 116.1 dBc across the entire DPLL operation range (3.2-4.8 GHz) thanks to design techniques. The measured in-band phase noise achieves 103 dBc at 100 kHz frequency offset and out-of-band phase noise of 122 dBc at 3 MHz frequency offset with integrated phase noise of 38.1 dBc from 10 kHz to 40 MHz.