Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <–103-dBc Spurious Tones Using Digital Spur Cancellation

In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional-
$N$
spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and simulation results to elucidate the associated design tradeoffs. Leveraging this novel spur cancellation approach, our synthesizer demonstrates exceptional performance, with results such as <90-fs integrated rms jitter and
$\lt -103$
-dBc spurious tones at a 2.48-GHz carrier frequency. A prototype IC with two FFSs, which can operate from 0.5 to 2.5 GHz, was fabricated in a 28-nm CMOS process to demonstrate the proposed spur cancellation technique. The digital core of FFS consumes 2.6 mW from 0.9-V supply with an area of 0.15 mm2.