A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation

A 2.4-GHz full-duplex (FD) transceiver, which employs multiple self-interference (SI) cancellation techniques, is presented for future wideband wireless communication. The proposed FD radio features broadband SI suppression, cancellers calibrated for enhanced linearity, and the ability to cancel long-delay spread SI. A prototype chip is fabricated in a Taiwan Semiconductor Manufacturing Company’s (TSMC) 40-nm CMOS process and works with a Xilinx RFSoC evaluation kit to complete the calibration loop for the radio analog front end (AFE). The FD AFE chip integrates an electrical-balanced duplexer (EBD) with a tuned impedance matching network (
${Z}$
Bal), two broadband five complex-tap continuous-time finite impulse response (FIR)-based RF cancellation filters, and a mixed-signal baseband cancellation path operating with a field-programmable gate array (FPGA) to complete a long-delay spread (
$\tau =+174$
ns) SI canceller. A fourth-order
${Z}$
Bal is employed to reduce SI group delay and improves the cancellation bandwidth (BW) when used with complex filters. This work reports a measured SI suppression of 62 dB across +120-MHz BW for delay spreads between 0 and 0.28 ns and SI cancellation of 23 dB across +120-MHz BW for delay spreads between 0.4 and 174 ns. The EBD achieves an enhanced common-mode rejection exceeding 55 dB through the use of a center-tap capacitor (
${C}$
CT) with minimal additional area. The RF canceller, calibrated by digitally controlled current digital-to-analog converters (DACs), demonstrates a maximum input-referred third order intercept point (IIP3) of +42 dBm. The receiver (RX) has a measured noise figure (NF) of 6.8 dB and an IIP3 of −21 dBm at the maximum gain setting of 40 dB. An integrated harmonic-rejection power amplifier (PA) achieves a measured maximum output power
${P}$
Sat and a PAE of 19.1 dBm and 27%, respectively. The overall FD transceiver, including an integrated phase-locked loop (PLL), occupies an area of 3.2 mm2 and consumes a total power of 373/78 mW including/excluding the PA.