A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2–0 MASH Delta-Sigma ADC

This article presents a fully dynamic 2–0 multistage noise-shaping (MASH) analog-to-digital converter (ADC) for low-power and high-precision applications. It implements the feedforward digitally with a 3-bit asynchronous successive-approximation-register (SAR) ADC and reuses it as the zeroth backend stage. Correlated level shifting (CLS) boosts the floating inverter amplifier (FIA) gain, embedded in the loop filter to implement integration. Dynamic body-biasing (DBB) technique helps boost the gain of a single-stage FIA with only one reservoir capacitor. Fabricated in 55-nm CMOS technology, the prototype ADC achieves measured SNDR of 94.0 and 96.9 dB dynamic range (DR) in 1-kHz BW at an oversampling ratio (OSR) of 125 while only consuming $2.87~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 179.4 dB and a DR-based FoM of 182.3 dB.

I. Introduction

Power-efficient analog-to-digital converters (ADCs) are in high demand for low-bandwidth, high-precision applications due to the unprecedentedly rapid development of smart sensors, health care, and Internet-of-Things (IoT).