Contents I. Introduction
Flourishing development of smart sensors and the Internet-of-Things (IoT) applications are strongly expecting high dynamic-range (DR) analog-to-digital converters (ADCs) with micro-power consumptions. Beneficial from oversampling and noise-shaping (NS), switched-capacitor (SC) modulators have already shown outstanding performance in this scenario for their dynamic operation, process robustness, and clock jitter immunity [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11]. Nevertheless, integrators based on power-hungry operational transconductance amplifiers (OTAs) are the bottleneck of power reduction [1], [2], [3], [4], [5], [6], [7]. Noise-shaping (NS) successive-approximation-register (NSSAR) ADCs combine the benefits of delta–sigma modulator (DSM) and SAR, demonstrating excellent power efficiency over a wide range of signal frequencies. However, the mitigation of element mismatch relies on either off-chip foreground calibration or on-chip methods like dynamic element matching (DEM) [12], which improve the linearity at the cost of indispensable digital logic overhead and mismatch error shaping (MES) [13], [14], [15], which is much efficient but requires compensation techniques to maintain the full-scale input range. Zoom ADCs also have gained popularity for the appropriate tradeoff among resolution, power, and design complexity. However, the signal to quantization noise ratio (SQNR) loss caused by the over ranging and the out-of-band interference are knotty issues [5], [6], [7].
