Analysis and Design of a 10.4-ENOB 0.92–5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications

Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power consumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/or processing power, making them well-suited for low-power edge applications. Current implementations are, however, limited in performance and power efficiency. Due to the asynchronous output stream, it is also difficult to interface such LCADCs with (conventional) clocked digital processing circuits/transmitters. This article introduces a new LCADC topology, with clocked comparators but with an adaptive clocking scheme. It has a low power consumption and can seamlessly be integrated with any type of processing/transmission circuit. This article first analyzes the major bottleneck to the power consumption of the classical continuous-time (CT) LCADCs. A new, more power-efficient topology with clocked comparators is then introduced. Thanks to the adaptive clocking algorithm, the power consumption scales with the signal activity. The discrete-time (DT) topology can achieve a
$10\times $
–
$100\times $
lower comparator power depending on the signal activity. A prototype IC with an 8-bit 15-kHz BW LCADC is implemented in a 40-nm CMOS technology. Measurement results show that the ADC has an activity-based power consumption from 0.92
$\mu \text{W}$
for an ECG signal to 5.38
$\mu \text{W}$
for a 15-kHz full-scale sine wave. The ADC has 10.4 ENOB and reaches a peak Walden FOM of 138 fJ/conv. For an ECG signal as input, the ADC can achieve a 30% reduction in data and a
$3\times $
reduction in ADC I/O power. This showcases how such LCADCs can yield significant benefits in edge systems.