I. Introduction
Fiber-optics have contributed greatly to the ever-increasing digital world: on the one hand, clusters of silica single-mode fibers (SMF), which can transmit hundreds of Gb/s carried on 1310/1550 nm light over distances of tens of kilometers, form the backbone of broadband internet connections. On the other hand, multi-mode fibers (MMF) facilitate cheaper 850 nm links at a reduced bandwidth-distance-product, thus providing an alternative to existing copper interconnects [1], [2] . Single-mode links are also being proposed for very short interchip optical connections since electrical channels can no longer support the increasing bandwidth requirements associated with I/O circuit performance scaling [3]. While fiber-optic links clearly provide better performance than copper, the major disadvantage is still the cost, which is dominated by the opto-electrical components rather than the fiber itself. Generally, the building blocks of these components, laser-driver and laser for transmitter and photodetector, transimpedance amplifier (TIA) and limiting amplifier for receiver, are each fabricated in their own dedicated process. While such a multi-chip implementation results in excellent performance for each block, it is far from ideal from a cost perspective. Additionally, side effects such as bonding inductances, ground-bounces and more stringent packaging have to be taken care of as well [4]. Integrating these components on a single chip would provide an elegant solution to this problem. Photonic integrated circuit (PIC) technologies can integrate optical components on chip, but in most PIC technologies transistors cannot be fabricated. These technologies must make use of copper pillar bonding with an electric integrated circuit (EIC), to obtain a full receiver/transmitter [5]–[7] , which increases the cost again. Monolithic chips fabricated in CMOS processes are the ultimate solution to reduce cost maximally. The majority of research in CMOS opto-electronic chips is focused on optical receivers in bulk CMOS processes [8]–[12] , arguably the most cost-effective technology of them all. Here, light is impinged from the topside of the chip (frontside illumination - FSI) straight onto a silicon (avalanche) PN-photodiode. As there is no light absorption for the 1310/1550 nm wavelengths due to the indirect and rather wide bandgap of silicon, these receivers are only suited for the 850 nm communication band. In silicon-on-insulator (SOI) CMOS technologies, a different kind of circuit can be realized: using a vertical grating coupler, light can be coupled into waveguides in the SOI. By forming PN-junctions in germanium, which is present in nanoscale CMOS technologies to strain silicon near the surface, 1310/1550 nm light can also be detected, enabling fully integrated receivers [13]. Furthermore, as optical microring resonators can also be integrated in SOI CMOS, this technology even offers fully integrated transceivers [14], [15]. However, the best performance is achieved when the process is custom modified for optimal photonic integration [16]–[18]. Although the germanium is present in bulk CMOS technologies as well, it must be noted that this layer is very thin and hardly any light is absorbed when surface-illuminated. Thus, PN-photodiodes cannot facilitate fully integrated 1310/1550 nm receivers in bulk CMOS. Recently, Schottky diodes in bulk CMOS have been demonstrated to detect both 850, 1310 and 1550 nm by means of internal photoemission [19], [20]. This paper will discuss these devices more extensively and explain how to integrate them in a full optical receiver. In Section II, the photodiode equivalent model is presented and discussed. General Schottky diode photodiode theory is layed out in Section III, while the fabricated 40 nm CMOS Schottky photodiodes are discussed in Section IV. In Section V the devices are modelled through measurements and finally, Section VI summarizes the performance of all measured Schottky photodiodes.