Analysis and Behavioral Modeling of Monolithic Digital Potentiometers

This paper focuses on analysis and modeling of complementary metal-oxide semiconductor (CMOS) resistive digitalto-analog converter (RDAC) potentiometers based on string digital-to-analog converter or Kelvin divider architecture. The model is developed by using very-high hardware description language (VHDL) analog and mixed-signal language, and accurately simulates basic static and dynamic parameters, integral nonlinearity, terminal voltage operating range, and leakage current at various operational modes for linear and nonlinear changing of the middle point (wiper). The model is implemented in the SystemVision simulation platform, using a style combining structural and behavioral elements. For verification of the model parameters are extracted for single-stage AD5235 and triple-stage AD5143 RDACs from analog devices as examples. The workability of the proposed models is validated by simulation and experimental testing of sample digitally controlled analog circuits. The comparative analysis shows that the achieved relative error, between the simulation and the experimental results at the maximum value of the nominal resistance equal to 25 kΩ, is less than 5%. Moreover, an error of 5% is quite acceptable, considering the technological tolerances of the parameters.