Asymmetrical Cascaded Multilevel Inverter Based on Transistor-Clamped H-Bridge Power Cell

This paper presents an asymmetrical cascaded multilevel inverter based on a five-level transistor-clamped H-bridge power cell. A two-cell configuration with a dc link voltage ratio of 4 : 1 is presented. The modulation method is based on the fundamental frequency switching. An analysis of the inverter output voltage and harmonics is presented. Injection of the third harmonic voltage as to maximize the output voltage and the issue of the inverse power flow or regeneration in the low-voltage cell are presented. The prototype of the proposed inverter was built, and its functionality was verified through experimental results.