Modified Synchronized SVPWM Strategies to Reduce CMV for Three-Phase VSIs at Low Switching Frequency

The high common-mode voltage (CMV) generated by conventional synchronized space vector pulsewidth modulation (SVPWM) strategies may lead to bearing failure and electromagnetic interference problems. However, existing CMV reduction methods are based on asynchronized SVPWM, which will cause unacceptable harmonic distortion at low switching frequency. In this article, four modified synchronized SVPWM (MS-SVPWM) strategies are presented to reduce the CMV and improve the output performance of three-phase voltage source inverters (VSIs) at low switching frequency. In the proposed methods, only nonzero vectors are employed to reduce CMV, and the constraint conditions of preserving three-phase, half-wave, and quarter-wave symmetries of PWM waveforms in terms of active vectors are established. A precorrection scheme is proposed and applied to the presented MS-SVPWM strategies to achieve an accurate output voltage of inverters. Moreover, the linearity characteristics of the output voltage, the harmonic performance of line-line voltage and CMV, and the stator flux trajectories of the proposed strategies are investigated and compared. Experimental results for a 2.2-kW induction motor fed by a two-level VSI are presented to illustrate the effectiveness of the proposed MS-SVPWM strategies.