Full-Loop Equivalent Circuit Model for Plasma-Induced Damage Simulation

In this paper, a new circuit model is proposed to simulate plasma-induced damage (PID). It includes the two sheaths of the plasma, the blocking capacitor, and the RF power source coupled with the victim device. As a result, this model accounts for both the ac behavior of the plasma and the local voltage imbalance induced by differences in shading factors. The advantage of this approach, compared with the previous works, is that it can yield the waveform impinged by the plasma on the transistor gate, which is known to influence the amount of reliability degradation experienced by the device. Finally, this model is also utilized to elucidate the impact of a parasitic capacitance connected to the transistor gate on the extent of the PID inflicted on the victim device.